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features ? single 2.7v - 3.6v supply serial peripheral inte rface (spi) compatible ? supports spi modes 0 and 3 33 mhz maximum clock frequency flexible, uniform erase architecture ? 4-kbyte blocks ? 32-kbyte blocks ? 64-kbyte blocks ? full chip erase optimized physical sectoring for code shadowing and code + data storage applications ? one 16-kbyte top boot sector ? two 8-kbyte sectors ? one 32-kbyte sector ? seven 64-kbyte sectors individual sector protection for program/erase protection hardware controlled locking of protected sectors byte program architecture with sequen tial byte progra m mode capability ? sequential byte program mode improves throughput for programming multiple bytes jedec standard manufacturer an d device id read methodology low power dissipation ? 7 ma active read current (typical) ? 15 a deep power-down current (typical) endurance: 100,000 program/erase cycles data retention: 20 years complies with full industrial temperature range industry standard green (pb/halide -free/rohs compliant) package options ? 8-lead soic ? 8-lead mlf 1. description the at26f004 is a serial interface flash memory device designed for use in a wide variety of high-volume consumer based applications in which program code is shad- owed from flash memory into embedded or ex ternal ram for execution. the flexible erase architecture of the at26f004, with it s erase granularity as small as 4 kbytes, makes it ideal for data storage as well, eliminating the need for additional data storage eeprom devices. the physical sectoring and the erase block sizes of the at26f004 have been opti- mized to meet the needs of today's code and data storage applications. by optimizing the size of the physical sectors and erase blocks, the memory space can be used much more efficiently. because certain code modules and data storage segments must reside by themselves in their own protected sectors, the wasted and unused memory space that occurs with large sectored and large block erase flash memory devices can be greatly reduced. this increa sed memory space efficiency allows addi- tional code routines and data storage segments to be adde d while still maintaining the same overall device density. 4-megabit 2.7-volt only serial firmware dataflash ? memory at26f004 3588c?dflash?04/06
2 3588c?dflash?04/06 at26f004 the at26f004 also offers a sophisticated met hod for protecting individual sectors against erroneous or malicious program and erase operations. by providing the ability to individually protect and unprotect sectors, a system can unprotect a specific sector to modify its contents while keeping the remaining sectors of the memory array securely protected. this is useful in applications where program code is patched or updated on a subroutine or module basis, or in applications where data storage segments need to be modified without running the risk of errant modifications to the program code segments. specifically designed for use in 3-volt systems, the at26f004 supports read, program, and erase operations with a supply voltage range of 2.7v to 3.6v. no separate voltage is required for programming and erasing. 2. pin descriptions and pinouts table 2-1. pin descriptions symbol name and function asserted state type cs chip select: asserting the cs pin selects the device. when the cs pin is deasserted, the device will be deselected and normally placed in standby mode (not deep power-down mode), and the so pin will be in a high-impedance state. w hen the device is deselected, data will not be accepted on the si pin. a high-to-low transition on the cs pin is required to start an oper ation, and a low-to-high transition is required to end an operation. when ending an internally self-timed operation such as a program or erase cycle, the device will not enter the standb y mode until the comple tion of the operation. low input sck serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command, address, and input data present on the si pin is always latched on the rising edge of sck, while output dat a on the so pin is always clocked out on the falling edge of sck. ? input si serial input: the si pin is used to shift data into the device. the si pin is used for all data input including command and address sequences. data on the si pin is always latched on the rising edge of sck. ? input so serial output: the so pin is used to shift data out fr om the device. data on the so pin is always clocked out on the falling edge of sck. ? output wp write protect: the wp pin controls the hardware locking feature of the device. refer to section ?protection commands and features? on page 13 for more details on protection features and the wp pin. the wp pin is not internally pulled-high and cannot be left floating. if hardware controlled locking will not be used, then the wp pin must be externally connected to v cc . low input hold hold: the hold pin is used to temporarily pause serial communication without deselecting or resetting the device. while the hold pin is asserted, transitions on the sck pin and data on the si pin will be ignored, and the so pin will be in a high-impedance state. the cs pin must be asserted, and the sck pin must be in the low state in order for a hold condition to start. a hold condition pauses serial communication only and does not have an effect on internally self-timed operations such as a pr ogram or erase cycle. please refer to section ?hold? on page 27 for additional details on the hold operation. the hold pin is not internally pulled-high and cannot be left floating. if the hold function will not be used, then the hold pin must be externally connected to v cc . low input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ?power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ?power
3 3588c?dflash?04/06 at26f004 3. block diagram 4. memory array to provide the greatest flexibilit y, the memory array of the at26f004 can be erased in four lev- els of granularity including a full chip erase. in addition, the array has been divided into physical sectors of various sizes, of which each sector can be individually protected from program and erase operations. the sizes of the physical sectors are optimized for both code and data storage applications, allowing both code and data segments to reside in their own isolated regions. the memory architecture diagram illustrates the breakdown of each erase level as well as the breakdown of each physical sector. figure 2-1. 8-soic top view figure 2-2. 8-mlf top view 1 2 3 4 8 7 6 5 cs so w p g n d v cc hold sck si cs so w p g n d v cc hold sck si 8 7 6 5 1 2 3 4 flash memory array y-gating control logic cs sck so si hold wp y-decoder address latch x-decoder i/o buffers and latches interface control and logic
4 3588c?dflash?04/06 at26f004 figure 4-1. memory architecture diagram internal s ectorin g for 64kb 3 2kb 4kb s ector protection block era s e block era s e block era s e function (d 8 h command) (52h command) (20h command) 4kb 7ffffh ? 7f000h 4kb 7efffh ? 7e000h 4kb 7dfffh ? 7d000h 4kb 7cfffh ? 7c000h 4kb 7bfffh ? 7b000h 4kb 7afffh ? 7a000h 4kb 79fffh ? 79000h 4kb 78fffh ? 78000h 4kb 77fffh ? 77000h 4kb 76fffh ? 76000h 4kb 75fffh ? 75000h 4kb 74fffh ? 74000h 4kb 73fffh ? 73000h 4kb 72fffh ? 72000h 4kb 71fffh ? 71000h 4kb 70fffh ? 70000h 4kb 6ffffh ? 6f000h 4kb 6efffh ? 6e000h 4kb 6dfffh ? 6d000h 4kb 6cfffh ? 6c000h 4kb 6bfffh ? 6b000h 4kb 6afffh ? 6a000h 4kb 69fffh ? 69000h 4kb 68fffh ? 68000h 4kb 67fffh ? 67000h 4kb 66fffh ? 66000h 4kb 65fffh ? 65000h 4kb 64fffh ? 64000h 4kb 63fffh ? 63000h 4kb 62fffh ? 62000h 4kb 61fffh ? 61000h 4kb 60fffh ? 60000h 4kb 0ffffh ? 0f000h 4kb 0efffh ? 0e000h 4kb 0dfffh ? 0d000h 4kb 0cfffh ? 0c000h 4kb 0bfffh ? 0b000h 4kb 0afffh ? 0a000h 4kb 09fffh ? 09000h 4kb 08fffh ? 08000h 4kb 07fffh ? 07000h 4kb 06fffh ? 06000h 4kb 05fffh ? 05000h 4kb 04fffh ? 04000h 4kb 03fffh ? 03000h 4kb 02fffh ? 02000h 4kb 01fffh ? 01000h 4kb 00fffh ? 00000h ran g e block addre ss block era s e detail 64kb (sector 0) 64kb (sector 6) 64kb 64kb 64kb 32kb 32kb 32kb 32kb 32kb 32kb 32kb (sector 7) 16kb (sector 10) 8kb (sector 9) 8kb (sector 8)
5 3588c?dflash?04/06 at26f004 5. device operation the at26f004 is controlled by a set of instructions that are sent from a host controller, com- monly referred to as the spi master. the spi master communicates with the at26f004 via the spi bus which is comprised of four signal lines: chip select (cs ), serial clock (sck), serial input (si), and serial output (so). the spi protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the sck polarity and phase and how the polarity and phase control the flow of data on the spi bus. the at26f004 supports the two most common modes, spi modes 0 and 3. the only difference between spi modes 0 and 3 is the polarity of the sck signal when in the inactive state (when the spi master is in standby mode and not transferring any data). with spi modes 0 and 3, data is always latched in on the rising edge of sck and always output on the falling edge of sck. figure 5-1. spi mode 0 and 3 6. commands and addressing a valid instruction or operat ion must always be started by first asserting the cs pin. after the cs pin has been asserted, the spi master must then clock out a valid 8-bit opcode on the spi bus. following the opcode, instruction dependent information such as address and data bytes would then be clocked out by the spi master. all opcode, address, and data bytes are transferred with the most significant bit (msb) first. an operation is ended by deasserting the cs pin. opcodes not supp orted by the at26f004 will be ignored by the device and no operation will be started. the device will continue to ignore any data pr esented on the si pin until the start of the next operation (cs pin being deasserted and then reasserted). in addition, if the cs pin is deas- serted before all eight bits of an opcode are sent to the device, then the device will simply return to the idle state and wait for the next operation. addressing of the device requires a total of three bytes of information to be sent, representing address bits a23 - a0. since the upper address limit of the at26f004 memory array is 07ffffh, address bits a23 - a19 are always ignored by the device. sck cs si so msb lsb msb lsb
6 3588c?dflash?04/06 at26f004 notes: 1. three address bytes are only required for the first opera tion to designate the address at which to start the programmin g. afterwards, the internal address counter automatically incr ements, so subsequent sequentia l program mode operations only require clocking in of the opcode and the data byte until the sequential pr ogram mode has been exited. table 6-1. command listing command opcode address bytes dummy bytes data bytes read commands read array 0bh 0000 1011 3 1 1+ read array (low frequency) 03h 0000 0011 3 0 1+ program and erase commands block erase (4 kbytes) 20h 0010 0000 3 0 0 block erase (32 kbytes) 52h 0101 0010 3 0 0 block erase (64 kbytes) d8h 1101 1000 3 0 0 chip erase 60h 0110 0000 0 0 0 c7h 1100 0111 0 0 0 byte program 02h 0000 0010 3 0 1 sequential byte program mode afh 1010 1111 3, 0 (1) 01 protection commands write enable 06h 0000 0110 0 0 0 write disable 04h 0000 0100 0 0 0 protect sector 36h 0011 0110 3 0 0 unprotect sector 39h 0011 1001 3 0 0 read sector protection registers 3ch 0011 1100 3 0 1+ status register commands read status register 05h 0000 0101 0 0 1+ write status register 01h 0000 0001 0 0 1 miscellaneous commands read manufacturer and device id 9fh 1001 1111 0 0 1 to 4 deep power-down b9h 1011 1001 0 0 0 resume from deep power-down abh 1010 1011 0 0 0
7 3588c?dflash?04/06 at26f004 7. read commands 7.1 read array the read array command can be used to sequentia lly read a continuous stream of data from the device by simply providi ng the sck signal once the initial starting address has been speci- fied. the device incorporates an internal address counter that automatically increments on every clock cycle. two opcodes, 0bh and 03h, can be used for the re ad array command. the use of each opcode depends on the maximum sck frequency that will be used to read data from the device. the 0bh opcode can be used at any sck frequency up to the maximum specified by f sck . the 03h opcode can be used for lower frequency read operations up to the maximum specified by f rdlf . to perform the read array operation, the cs pin must first be asserted and the appropriate opcode (0bh or 03h) must be clocked into the device. after the opcode has been clocked in, the three address bytes must be clocked in to specify the starting address location of the first byte to read within the memory array. if the 0bh opcode is used, then one don't care byte must also be clocked in after the three address bytes. after the three address bytes (and the one don't care byte if using opcode 0bh) have been clocked in, additional clock cycles will result in se rial data being output on the so pin. the data is always output with the msb of a byte first. when the last byte (07ffffh) of the memory array has been read, the device will cont inue reading back at the beginn ing of the array (000000h). no delays will be incurred when wrapping around from the end of the array to the beginning of the array. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. figure 7-1. read array - 0bh opcode figure 7-2. read array - 03h opcode sck cs si so msb msb 23 1 0 00001011 67 5 41011 9 8 12 39 42 43 41 40 37 3 8 33 36 35 34 31 32 29 30 44 47 4 8 46 45 opcode aaaa aaa aa msb xxxxxxxx msb msb dddddddd d d address bits a23-a0 do n' t care data byte 1 high-impeda n ce sck cs si so msb msb 23 1 0 00000011 67 5 41011 9 8 12 37 3 8 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa aa msb msb dddddddd d d address bits a23-a0 data byte 1 high-impeda n ce
8 3588c?dflash?04/06 at26f004 8. program and erase commands 8.1 byte program the byte program command allows a single byte of data to be programmed into a previously erased memory location. an erased memory location is one that has all eight bits set to the logi- cal ?1? state (a byte value of ffh). before a byte program command can be started, the write enable command must have been previously issued to the device (see ?write enable? on page 13 ) to set the write enable latch (wel) bit of the status register to a logical ?1? state. to perform a byte program command, an opcode of 02h must be clocked into the device fol- lowed by the three address bytes denoting which byte location of the memory array to program. after the address bytes have been clocked in, the nex t byte of data clocked into the device will be latched internally. if more than one byte of data is clocked in, then only the first byte of data sent on the si pin will be stored in the internal latches and all subsequen t bytes will be ignored. when the cs pin is deasserted, the device will take the one byte stored in the internal latches and program it into the memory array location specified by a23 - a0. the programming of the byte is internally self-timed and should take place in a time of t bp . the three address bytes and a complete byte of data must be clocked into the device before the cs pin is deasserted; other- wise, the device will ab ort the operation and no data will be programmed into the memory array. in addition, if the address specified by a23 - a0 points to a memory location within a sector that is in the protected state (see ?protect sector? on page 15 ), then the byte program command will not be executed, and the device will return to the idle state once the cs pin has been deas- serted. the wel bit in the status register will be reset back to the logical ?0? state if the program cycle aborts due to an incomplete address being sent, an incomplete byte of data being sent, or because the memory location to be programmed is protected. while the device is programming, the status r egister can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled rather than waiting the t bp time to determine if the byte has finished programming. at some point before the program cycle complete s, the wel bit in the status r egister will be reset back to the logical ?0? state. the byte program mode is the default programming mode after the device powers-up or resumes from a device reset. figure 8-1. byte program sck cs si so msb msb 23 1 0 00000010 67 5 41011 9 812 39 37 38 33 36 35 34 31 32 29 30 opcode high-impedance aaaa aaa a a msb ddddddd d address bits a23-a0 data in
9 3588c?dflash?04/06 at26f004 8.2 sequential byte program mode the sequential byte program mode improves throughput over the single byte program opera- tion when programming multiple bytes of data into consecutive address locations. when using the sequential byte programming mode, an inter nal address counter keeps track of the byte location to program, thereby eliminating the need to supply an address sequence to the device for every byte to program. all address locations to be programmed using the sequential byte program mode must be in the erased state. before the sequential byte program mode can first be entered, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. to start the sequential byte program mode, the cs pin must first be asserted, and the opcode of afh must be clocked into the device. for the first program cycle, three address bytes must be clocked in after the opcode to designate the first byte location to program. after the address bytes have been clocked in, the nex t byte of data clocked into the device will be latched inter- nally. deasserting the cs pin will start the internally self-timed program operation, and the first byte will be programmed into the memory location specified by a23 - a0. after the first byte has been successfully programmed, a second byte can be programmed by simply reasserting the cs pin, clocking in the afh opcode, and then clocking in the next byte of data. when the cs pin is deasserted, the second byte of data will be prog rammed into the next sequential memory location. the process would be repeated for any additional bytes. there is no need to reissue the write enable command once the sequential byte program mode has been entered. when the last desired byte has been programmed into the memory array, the sequential byte program mode operation can be terminated by reasserting the cs pin and sending the write disable command to the device to reset the wel bit in the status register back to the logical ?0? state. if more than one byte of data is ever clocked in during each program cycle, then only the first byte of data sent on the si pin will be stored in the inte rnal latches and all subsequent bytes will be ignored. the programming of each byte is inte rnally self-timed and should take place in a time of t bp . for each program cycle, a complete byte of data must be clocked into the device before the cs pin is deasserted; otherwise, the device w ill abort the operation, the byte of data will not be programmed into the memory array, and the wel bit in the status register will be reset back to the logical ?0? state. if the address initially sp ecified by a23 - a0 points to a memory location within a sector that is in the protected state, then th e sequential byte pr ogram mode co mmand will not be executed, and the device will return to th e idle state once the cs pin has been deasserted. the wel bit in the status register will also be rese t back to the lo gical ?0? state. there is no address wrapping when using the sequential byte program mode. therefore, when the last byte (07ffffh) of the memory arra y has been programmed, the device will automati- cally exit the sequential byte program mode and reset the wel bit in the status register back to the logical ?0? st ate. in addition, the seque ntial byte program mode will not automatically skip over protected sectors; therefore, once the highest unprotected memory location in a program- ming sequence has been programmed, the device w ill automatically exit the sequential byte program mode and reset the wel bit in the status register. for example, if sector 1 was pro- tected and sector 0 was currently being programmed, once the last byte of sector 0 was programmed, the sequential byte program mode would automatically end. to continue pro- gramming with sector 2, the sequential byte program mode would have to be restarted by supplying the afh opcode, the three address bytes, and the first byte of sector 2 to program.
10 3588c?dflash?04/06 at26f004 while the device is programming a byte, the status register ca n be read and will indicate that the device is busy. for faster throughput, it is recommended that the status register be polled at the end of each program cycle rather than waiting the t bp time to determine if the byte has fin- ished programming before starting the next sequential byte program mode cycle. figure 8-2. sequential byte program mo de ? status register polling figure 8-3. sequential byte program mode ? waiting maximum byte program time cs si so afh a 23-16 a 15-8 a 7-0 05h data high-impedance afh data 05h 04h afh data 05h status register data status register data status register data seqeuntial program mode command first address to program status register read command write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) cs si so afh a 23-16 a 15-8 a 7-0 data high-impedance afh data 04h afh data seqeuntial program mode command first address to program write disable command seqeuntial program mode command seqeuntial program mode command note: each transition shown for si represents one byte (8 bits) t bp t bp t bp
11 3588c?dflash?04/06 at26f004 8.3 block erase a block of 4 kbytes, 32 kbytes, or 64 kbytes can be erased (all bits set to the logical ?1? state) in a single operation by using one of three diffe rent opcodes for the block erase command. an opcode of 20h is used for a 4-kbyte erase, an opcode of 52h is used for a 32-kbyte erase, and an opcode of d8h is used for a 64-kbyte erase. before a block erase command can be started, the write enable command must have been previously issued to the device to set the wel bit of the status register to a logical ?1? state. to perform a block erase, the cs pin must first be asserted and the appropriate opcode (20h, 52h or d8h) must be clocked into the device. after the opcode has been clocked in, the three address bytes specifying an address within the 4-kbyte, 32-kbyte, or 64-kbyte block to be erased must be clocked in. any additional data clocked into the device will be ignored. when the cs pin is deasserted, the device will erase the appropriate block. the erasing of the block is internally self-timed and should take place in a time of t blke . since the block erase command erases a region of bytes, the lower order address bits do not need to be decoded by the devi ce. therefore, fo r a 4-kbyte erase, addr ess bits a11 - a0 will be ignored by the device and their values can be either a logical ?1? or ?0?. for a 32-kbyte erase, address bits a14 - a0 will be ignored, and for a 64-kbyte erase, address bits a15 - a0 will be ignored by the device. despite the lower order address bits not being decoded by the device, the complete three address byte s must still be clocked into the device before the cs pin is deas- serted; otherwise, the device will abort the operation and no erase operati on will be performed. if the address specified by a23 - a0 points to a memory location within a sector that is in the pro- tected state, then the block erase command will not be executed, and th e device will return to the idle state once the cs pin has been deasserted. in addition, with the larger block erase sizes of 32 kbytes and 64 kbytes, more than one physical sector may be erased (e.g. sectors 10, 9 and 8) at one time. therefore, in order to erase a larger block that may span more than one sector, all of the sectors in the span must be in the unprotected state. if one of the physical sec- tors within the span is in t he protected state, then the dev ice will ignore the block erase command and will return to th e idle state once the cs pin is deasserted. the wel bit in the status register will be reset back to the logical ?0? state if the erase cycle aborts due to an incomplete address being sent or because a memory location within the region to be erased is protected. while the device is executing a successful erase cycle, the status regist er can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t blke time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. figure 8-4. block erase sck cs si so msb msb 23 1 0 cccccccc 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
12 3588c?dflash?04/06 at26f004 8.4 chip erase the entire memory array can be erased in a single operation by using the chip erase command. before a chip erase command can be started, the write enable command must have been pre- viously issued to the device to set the wel bit of the status register to a logical ?1? state. two opcodes, 60h and c7h, can be used for the chip erase command. there is no difference in device functionality when utilizin g the two opcodes, so they c an be used interchangeably. to perform a chip erase, one of the two opcodes (60h or c7h) must be clocked into the device. since the entire memory array is to be erased, no address bytes need to be clocked into the device, and any data clocked in after the opcode will be i gnored. when the cs pin is deasserted, the device will erase the entire memory array. the erasing of the device is internally self-timed and should take place in a time of t chpe . the complete opcode must be clocked into the device before the cs pin is deasserted; other- wise, no erase will be performed. in addition, if any sector of the memory array is in the protected state, then th e chip erase command will not be exec uted, and the device will return to the idle state once the cs pin has been deasserted. the wel bit in the status register will be reset back to the logical ?0? state if a sector is in the protected state. while the device is executing a successful erase cycle, the status regist er can be read and will indicate that the device is busy. for faster throughput, it is recommended that the status regis- ter be polled rather than waiting the t chpe time to determine if the device has finished erasing. at some point before the erase cycle completes, the wel bit in the status register will be reset back to the logical ?0? state. figure 8-5. chip erase sck cs si so msb 23 1 0 cccccccc 67 5 4 opcode high-impedance
13 3588c?dflash?04/06 at26f004 9. protection commands and features 9.1 write enable the write enable command is used to set the write enable latch (wel) bit in the status regis- ter to a logical ?1? state. the wel bit must be set before a program, erase, protect sector, unprotect sector, or write status register co mmand can be executed. this makes the issuance of these commands a two step process, thereby reducing the chances of a command being accidentally or erroneously executed. if the wel bi t in the status register is not set prior to the issuance of one of thes e commands, then the comma nd will not be executed. to issue the write enable command, the cs pin must first be asserted and the opcode of 06h must be clocked into the device. no address by tes need to be clocked into the device, and any data clocked in afte r the opcode will be ig nored. when the cs pin is deasserted, the wel bit in the status register will be set to a logical ?1?. the complete opcode must be clocked into the device before the cs pin is deasserted; otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-1. write enable sck cs si so msb 23 1 0 00000110 67 5 4 opcode high-impedance
14 3588c?dflash?04/06 at26f004 9.2 write disable the write disable command is used to reset the write enable latch (wel) bit in the status reg- ister to the logical ?0? state. with the wel bit re set, all program, erase, protect sector, unprotect sector, and write status regi ster commands will not be execut ed. the write disable command is also used to exit the sequential program mo de. other conditions can also cause the wel bit to be reset; for more details, refer to the ?wel bit? on page 20 . to issue the write disable command, the cs pin must first be asserted and the opcode of 04h must be clocked into the device. no address by tes need to be clocked into the device, and any data clocked in afte r the opcode will be ig nored. when the cs pin is deasserted, the wel bit in the status register will be reset to a logical ?0 ?. the complete opcode mu st be clocked into the device before the cs pin is deasserted; otherwise, the device will abort the operation and the state of the wel bit will not change. figure 9-2. write disable sck cs si so msb 23 1 0 00000100 67 5 4 opcode high-impedance
15 3588c?dflash?04/06 at26f004 9.3 protect sector every physical sector of the devi ce has a corresponding single-bit sector protection register that is used to control the software protection of a sector. upon device power-up or after a device reset, each sector protec tion register will default to the logi cal ?1? state indicating that all sectors are protected and cannot be programmed or erased. issuing the protect se ctor command to a particular sector address will set the corresponding sector protection register to the logical ?1? st ate. the following table outlines the two states of the sector protection registers. before the protect sector command can be issued, the write enable command must have been previously issued to set the wel bi t in the status register to a logical ?1?. to issue the protect sector command, the cs pin must first be asserted and the opcode of 36h must be clocked into the device followed by three address bytes designating any address within the sector to be locked. any additional data clocked into the device will be ignored. when the cs pin is deas- serted, the sector protection register co rresponding to the physical sector addressed by a23 - a0 will be set to the logical ?1? state, and the sector itself will then be protected from pro- gram and erase operations . in addition, the wel bit in the st atus register w ill be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted; otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous protecting or unprotecting of sectors, the sector protection registers can themselves be locked fr om updates by using the sprl (sector protec- tion registers locked) bit of the status register (refer to ?status register commands? on page 19 for more details). if the sector protection registers are locked, then any attempts to issue the protect sector command will be i gnored, and the device will reset the wel bit in the status reg- ister back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-3. protect sector table 9-1. sector protection register values value sector protection status 0 sector is unprotected and can be programmed and erased. 1 sector is protected and cannot be programm ed or erased. this is the default state. sck cs si so msb msb 23 1 0 00110110 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
16 3588c?dflash?04/06 at26f004 9.4 unprotect sector issuing the unprotect sector co mmand to a particular sector ad dress will reset the correspond- ing sector protection register to the logical ?0? state (see table 9-1 for sector protection register values). every physical sector of the device has a corresponding single-bit sector pro- tection register that is used to control the software protection of a sector. before the unprotect sector command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the unprotect sector command, the cs pin must first be asserted and the opcode of 39h must be clocked into the device. after the opcode has been clocked in, the three address bytes designat- ing any address within the sector to be unlocked must be clocked in. any additional data clocked into the device after the address bytes will be ignored. when the cs pin is deasserted, the sec- tor protection register corresponding to the sect or addressed by a23 - a0 will be reset to the logical ?0? state, and the sector itself will be unprotected. in addition, the wel bit in the status register will be reset back to the logical ?0? state. the complete three address bytes must be clocked into the device before the cs pin is deas- serted; otherwise, the device will abort the operation, the state of the sector protection register will be unchanged, and the wel bit in the status register will be reset to a logical ?0?. as a safeguard against accidental or erroneous locking or unlocking of sectors, the sector pro- tection registers can themselves be locked from updates by using the sprl (sector protection registers locked) bit of the status register (refer to ?status register commands? on page 19 for more details). if the sector protection regi sters are locked, then any attempts to issue the unprotect sector command will be i gnored, and the device will rese t the wel bit in the status register back to a logical ?0? and return to the idle state once the cs pin has been deasserted. figure 9-4. unprotect sector sck cs si so msb msb 23 1 0 00111001 67 5 41011 9 812 31 29 30 27 28 26 opcode aaaa aaa a a a a a address bits a23-a0 high-impedance
17 3588c?dflash?04/06 at26f004 9.5 read sector pr otection registers the sector protection registers can be read to determine the current software protection status of each sector. reading the se ctor protection registers, how ever, will not determine the status of the wp pin. to read the sector protection register for a particular sector, the cs pin must first be asserted and the opcode of 3ch must be clocked in. once the opcode has been clocked in, three address bytes designating any address withi n the sector must be clocked in. after the last address byte has been clocked in, the device will begin output ting data on the so pin during every subse- quent clock cycle. the data being output will be a repeating byte of either ffh or 00h to denote the value of the appropriate sector protection register. deasserting the cs pin will terminate the read operation and put the so pin into a high-imped- ance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. in addition to reading the individual sector pr otection registers, the software protection status (swp) bit in the status register can be read to determine if all, some, or none of the sectors are software protected (refer ?status register commands? on page 19 for more details). figure 9-5. read sector protection register table 9-2. read sector protection register ? output data output data sector protection register value 00h sector protection register value is 0 (sector is unprotected). ffh sector protection register va lue is 1 (sector is protected). sck cs si so msb msb 23 1 0 00111100 67 5 41011 9 812 3738 33 36 35 34 31 32 29 30 39 40 opcode aaaa aaa a a msb msb ddddddd d d d address bits a23-a0 data byte high-impedance
18 3588c?dflash?04/06 at26f004 9.6 protected states and th e write protect (wp ) pin the wp pin is not linked to the memory array itself and has no direct effect on the protection sta- tus of the memory array. instead, the wp pin, in conjunction with the sprl (sector protection registers locked) bit in the status register, is used to control the hardware locking mechanism of the device. for hardware locking to be active, two conditions must be met-the wp pin must be asserted and the sprl bit must be in the logical ?1? state. when hardware locking is active, the sector protection registers are locked and the sprl bit itself is also locked. therefore, sectors that are protected will be locked in the protected state, and sectors that are unprotected will be locked in the unprotecte d state. these states cannot be changed as long as hardware locking is active, so the protect sector, unprotect sector, and write status register commands will be ignored. in order to modi fy the protection status of a sector, the wp pin must first be deasserted, and the sprl bit in the status register must be reset back to the logical ?0? state. if the wp pin is permanently connected to gnd, then once the sprl bit is set to a logical ?1?, the only way to reset the bit back to the logical ?0? state is to power-cycle or reset the device. this allows a system to power-up with all sectors software protected but not hardware locked. therefore, sectors can be unprotected and protected as needed and then hardware locked at a later time by simply setting the sprl bit in the status register. when the wp pin is deasserted, or if the wp pin is permanently connected to vcc, the sprl bit in the status regist er can still be set to a logical ?1? to lo ck the sector protec tion registers. this provides a software locking ability to prevent erro neous protect sector or unprotect sector com- mands from being processed. tables 9-3 and 9-4 detail the various protection and locking states of the device. note: 1. ?n? represents a sector number table 9-3. software protection wp sector protection register n (1) sector n (1) x (don't care) 0unprotected 1protected table 9-4. hardware and software locking wp sprl locking sprl sector protection registers 00 ? can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands 01 hardware locked locked locked in current state. protect and unprotect sector commands will be ignored. 10 ? can be modified from 0 to 1 unlocked and modifiable using the protect and unprotect sector commands 11 software locked can be modified from 1 to 0 locked in current state. protect and unprotect sector commands will be ignored.
19 3588c?dflash?04/06 at26f004 10. status register commands 10.1 read status register the status register can be read to determine the device's ready/busy status, as well as the sta- tus of many other functions such as hardware locking and software protection. the status register can be read at any time, including dur ing an internally self-timed program or erase operation. to read the status register, the cs pin must first be asserted and the opcode of 05h must be clocked into the device. after t he last bit of the opcode has b een clocked in, the device will begin outputting status register data on the so pin during every subsequent clock cycle. after the last bit (bit 0) of the status regi ster has been clocked out, the se quence will repeat itself starting again with bit 7 as long as the cs pin remains asserted and the sck pin is being pulsed. the data in the status regi ster is constantly be ing updated, so each repe ating sequence will output new data. deasserting the cs pin will terminate the read status register operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. notes: 1. bit 7 of the status register is the only bit that can be user modified 2. r/w = readable and writable r = readable only table 10-1. status register format bit (1) name type (2) description 7 sprl sector protection registers locked r/w 0 1 sector protection registers are unlocked (default). sector protection registers are locked. 6 spm sequential program mode status r 0 1 byte programming mode (default). sequential programming mode entered. 5 res reserved for future use r 0 reserved for future use. 4wpp write protect (wp ) pin status r 0 1 wp is asserted. wp is deasserted. 3:2 swp software protection status r 00 01 10 11 all sectors are software unprotected. some sectors are software protected. read sector protection registers. reserved for future use. all sectors are software protected (default). 1 wel write enable latch status r 0 1 device is not write enabled (default). device is write enabled. 0 rdy/bsy ready/busy status r 0 1 device is ready. device is busy with an internal operation.
20 3588c?dflash?04/06 at26f004 10.1.1 sprl bit the sprl bit is used to control whether the sector protection registers can be modified or not. when the sprl bit is in the logical ?1? state, all sector protection registers are locked and can- not be modified with the protect sector and un protect sector commands (the device will ignore these commands). any sectors that are presently protected will remain protected, and any sec- tors that are presen tly unprotected will remain unprotected. when the sprl bit is in the logical ?0? state, all sector protection registers are unlocked and can be modified (the protect sector and unpr otect sector commands w ill be processed as nor- mal). the sprl bit defaults to the logical ?0? state after a power-up or a device reset. the sprl bit can be modified freely whenever the wp pin is deasserted. however, if the wp pin is asserted, then the sprl bit may only be changed from a logical ?0? (sector protection regis- ters are unlocked) to a logical ?1? (sector protection registers are locked). in order to reset the sprl bit back to a logical ?0? using the write status register command, the wp pin will have to first be deasserted. the sprl bit is the only bit of the status register than can be user modified via the write status register command. 10.1.2 spm bit the spm bit indicates whether the device is in the byte program mode or the sequential pro- gram mode. the default state after power-up or device reset is the byte program mode. 10.1.3 wpp bit the wpp bit can be read to determine if the wp pin has been asserted or not. 10.1.4 swp bits the swp bits provide feedback on the software protection status for the device. there are three possible combinations of the swp bits that indicate whether none, some, or all of the sectors have been protected using the protect sector command. if the swp bits indicate that some of the sectors have been protected, then the individual sector protection registers can be read with the read sector protection registers command to determine which sectors are in fact protected. 10.1.5 wel bit the wel bit indicates the current status of the internal write enable latch. when the wel bit is in the logical ?0? state, the device will not accept any program, erase, pr otect sector, unprotect sector, or write status register commands. the wel bit defaults to the logical ?0? state after a device power-up or reset. in addi tion, the wel bit will be reset to the logical ?0? state automati- cally under the following conditions: write disable operation completes successfully write status register operation completes successfully or aborts protect sector operation completes successfully or aborts unprotect sector operation completes successfully or aborts byte program operation completes successfully or aborts sequential program mode reaches highest unprotected memory location sequential program mode reaches the end of the memory array sequential program mode aborts
21 3588c?dflash?04/06 at26f004 block erase operation completes successfully or aborts chip erase operation completes successfully or aborts if the wel bit is in the logical ?1? state, it will not be reset to a logical ?0? if an operation aborts due to an incomplete or unrecognized opcode being clocked into the device before the cs pin is deasserted. in order for the wel bit to be reset when an operation aborts prematurely, the entire opcode for a program, erase, protect sector, unprotect sector, or write status register com- mand must have been clocked into the device. 10.1.6 rdy/bsy bit the rdy/bsy bit is used to determi ne whether or not an internal operation, such as a program or erase, is in progress. to po ll the rdy/bsy bit to detect the co mpletion of a pr ogram or erase cycle, new status register data must be contin ually clocked out of the device until the state of the rdy/bsy bit changes from a logical ?1? to a logical ?0?. figure 10-1. read status register sck cs si so msb 23 1 0 00000101 67 5 41011 9 812 2122 17 20 19 18 15 16 13 14 23 24 opcode msb msb dddddd d d d d msb ddddd d d d status register data status register data high-impedance
22 3588c?dflash?04/06 at26f004 10.2 write status register the write status register command is used to modify the sprl bit of the status register. before the write status register command can be issued, the write enable command must have been previously issued to set the wel bit in the status register to a logical ?1?. to issue the write status register command, the cs pin must first be asserted and the opcode of 01h must be clocked into the device. after t he opcode has been clocked in, one byte of data comprised of the sprl bit value and seven don' t care bits must be clocked in. any additional data bytes that are s ent to the device will be ignored. when the cs pin is deasserted, the sprl bit in the status register will be modified, and the wel bit in t he status register will be reset back to a logical ?0?. the complete one byte of data must be clocked into the device before the cs# pin is deasserted; otherwise , the device will abort the operation, the state of the sprl bit will not change, and the wel bit in the status re gister will be reset back to the logical ?0? state. if the wp pin is asserted, then the sprl bit can only be set to a logical ?1?. if an attempt is made to reset the sprl bit to a logical ?0? while the wp pin is asserted, then the write status register command will be ignored, a nd the wel bit in the status regist er will be reset back to the logical ?0? state. in order to reset the sprl bit to a logical ?0?, the wp pin must be deasserted. figure 10-2. write status register sck cs si so msb 23 1 0 0000000 67 5 41011 9 81415 13 12 opcode msb 1dxxxxx x x status register in high-impedance
23 3588c?dflash?04/06 at26f004 11. other commands and functions 11.1 read manufacturer and device id identification information can be read from the dev ice to enable systems to electronically query and identify the device while it is in system. the identification method and the command opcode comply with the jedec standard for ?manufacturer and device id read methodology for spi compatible serial interface memory devices?. the type of information that can be read from the device includes the jedec defined manufacturer id, the vendor specific device id, and the ven- dor specific extended device information. to read the identification information, the cs pin must first be asserted and the opcode of 9fh must be clocked into the device. after the opc ode has been clocked in, the device will begin out- putting the identification data on the so pin during the subsequent cloc k cycles. the first byte that will be output will be the manufacturer id followed by two bytes of device id information. the fourth byte output will be the extended device in formation stri ng length, which will be 00h indicating that no extended device information follows. after the extended device information string length byte is output, the so pin will go into a high-i mpedance state; ther efore, additional clock cycles will have no affect on the so pi n and no data will be output. as indicated in the jedec standard, reading the extended device information string length and any subsequent data is optional. deasserting the cs pin will terminate the manufacturer and device id read operation and put the so pin into a high-impedance state. the cs pin can be deasserted at any time and does not require that a full byte of data be read. table 11-1. manufacturer and device id information byte no. data type value 1 manufacturer id 1fh 2 device id (part 1) 04h 3 device id (part 2) 00h 4 extended device information string length 00h
24 3588c?dflash?04/06 at26f004 figure 11-1. read manufacturer and device id table 11-2. manufacturer and device id details data type bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value details manufacturer id jedec assigned code 1fh jedec code: 0001 1111 (1fh for atmel) 00011111 device id (part 1) family code density code 04h family code: 000 (at26fxxx series) density code: 00100 (4-mbit) 00000100 device id (part 2) mlc code product version code 00h mlc code: 000 (1-bit/cell technology) product version: 00000 (initial version) 00000000 sck cs si so 6 0 9fh 8 7 38 opcode 1fh 04h 00h 00h manufacturer id device id byte 1 device id byte 2 extended device information string length high-impedance 14 16 15 22 24 23 30 32 31 note: each transition shown for si and so represents one byte (8 bits)
25 3588c?dflash?04/06 at26f004 11.2 deep power-down during normal operation, the device will be placed in the standby mode to consume less power as long as the cs pin remains deasserted and no internal operation is in progress. the deep power-down command offe rs the ability to place the device into an even lower power consump- tion state called the deep power-down mode. when the device is in the deep power-down mo de, all commands including the read status register command will be ignored with the exception of the re sume from deep power-down command. since all commands will be ignored, the mode can be used as an extra protection mechanism against program and erase operations. entering the deep power-down mode is accomplished by simply asserting the cs pin, clocking in the opcode of b9h, and then deasserting the cs pin. any additional data clocked into the device after the opcode will be igno red. when the cs pin is deasserted, the device will enter the deep power-down mode within the maximum time of t edpd . the complete opcode must be clocked in before the cs pin is deasserted; otherwise, the device will abort the operation and return to the standby mode once the cs pin is deasserted. in addi- tion, the device will default to the standby mode after a po wer-cycle or a device reset. the deep power-down command will be ignored if an internally self-timed operation such as a program or erase cycle is in progress. the deep power-down command must be reissued after the internally self-timed operation has been completed in order for the device to enter the deep power-down mode. figure 11-2. deep power-down sck cs si so msb i cc 23 1 0 10111001 67 5 4 opcode high-impedance standby mode current active current deep power-down mode current t edpd
26 3588c?dflash?04/06 at26f004 11.3 resume from deep power-down in order exit the deep power-down mode and resume normal device operation, the resume from deep power-down command must be issued. the resume from deep power-down com- mand is the only command that the device will re cognize while in the d eep power-do wn mode. to resume from the deep power-down mode, the cs pin must first be asserted and opcode of abh must be clocked into the device. any addi tional data clocked into the device after the opcode will be ignored. when the cs pin is deasserted, the device will exit the deep power- down mode within the maximum time of t rdpd and return to the standby mode. after the device has returned to the standby mode, normal command operations such as read array can be resumed. if the complete opcode is not clocked in before the cs pin is deasserted, then the device will abort the operation and return to the deep power-down mode. figure 11-3. resume from deep power-down sck cs si so msb i cc 23 1 0 10101011 67 5 4 opcode high-impedance deep power-down mode current active current standby mode current t rdpd
27 3588c?dflash?04/06 at26f004 11.4 hold the hold pin is used to pause the serial communic ation with the device without having to stop or reset the clock sequence. the hold mode, however, does not have an affect on any internally self-timed operations such as a program or eras e cycle. therefore, if an erase cycle is in progress, asserting the hold pin will not pause the operation, and the erase cycle will continue until it is finished. the hold mode can only be entered while the cs pin is asserted. the hold mode is activated simply by asserting the hold pin during the sck low pulse. if the hold pin is asserted during the sck high pulse, then the hold mode won't be started until the beginning of the next sck low pulse. the device will remain in the hold mode as long as the hold pin and cs pin are asserted. while in the hold mode, the so pi n will be in a high-impedance state. in addition, both the si pin and the sck pin will be ignored. the wp pin, however, can still be asserted or deasserted while in the hold mode. to end the hold mode and resume serial communication, the hold pin must be deasserted during the sck low pulse. if the hold pin is deasserted during the sck high pulse, then the hold mode won't end until the beginning of the next sck low pulse. if the cs pin is deasserted while the hold pin is still asserted, then the hold mode will abort and the device may abort the current operation depending on whether or not a complete opcode, address bytes, or data byte was already clocked into the device before the hold mode was entered. the wel bit in the status register wil l be reset back to a logical ?0? if a program, erase, protect sector, unprotect sector, or write status register operation aborts as a result of the hold mode aborting. figure 11-4. hold mode sck cs hold hold hold hold
28 3588c?dflash?04/06 at26f004 12. electrical specifications 12.1 absolute maximum ratings* temperature under bias .... ........... ............ ..... -55 c to +125 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground .....................................-0.6v to +4.1v all output voltages with respect to ground .............................-0.6v to v cc + 0.5v 12.2 dc and ac operating range at26f004 operating temperature (case) industrial -40 c to 85 c v cc power supply 2.7v to 3.6v 12.3 dc characteristics symbol parameter condition min typ max units i sb standby current cs , wp , hold = v cc , all inputs at cmos levels 25 35 a i dpd deep power-down current cs , wp , hold = v cc , all inputs at cmos levels 20 25 a i cc1 active current, read operation f = 33 mhz; i out = 0 ma; cs = v il , v cc = max 812 ma f = 20 mhz; i out = 0 ma; cs = v il , v cc = max 710 i cc2 active current, program operation cs = v cc , v cc = max 9 12 ma i cc3 active current, erase operation cs = v cc , v cc = max 9 12 ma i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol output low voltage i ol = 1.6 ma; v cc = min 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2v v
29 3588c?dflash?04/06 at26f004 notes: 1. specification only applies when using the 03h read array (low frequency) command. 2. not 100% tested (value guaranteed by design and characterization). 3. specification only applies when using the spi mode 3 timing. 4. only applicable as a constraint for the write status register command when sprl = 1. 12.4 ac characteristics symbol parameter min max units f sck serial clock (sck) frequency 33 mhz f rdlf sck frequency for read array (low frequency ? 03h opcode) 20 mhz t sckh sck high time 13 20 (1) ns t sckl sck low time 13 20 (1) ns t sckr (2) sck rise time, peak-to-peak (slew rate) 0.1 v/ns t sckf (2) sck fall time, peak-to-peak (slew rate) 0.1 v/ns t csh chip select high time 50 ns t csls chip select low setup time (relative to sck) 5 ns t cslh chip select low hold time (relative to sck) 5 12 (3) ns t cshs chip select high setup ti me (relative to sck) 5 ns t cshh chip select high hold time (relative to sck) 5 ns t ds data in setup time 3 ns t dh data in hold time 3 ns t oh output hold time 0 ns t dis (2) output disable time 10 ns t v output valid time 12 18 (1) ns t hls hold low setup time (relative to sck) 5 ns t hlh hold low hold time (relative to sck) 5 ns t hhs hold high setup time (relative to sck) 5 ns t hhh hold high hold time (relative to sck) 5 ns t hlqz (2) hold low to output high-z 9 ns t hhqx (2) hold high to output low-z 9 ns t wps (2)(4) write protect setup time 20 ns t wph (2)(4) write protect hold time 100 ns t secp (2) sector protect time (fro m chip select high) 20 ns t secup (2) sector unprotect time (from chip select high) 20 ns t edpd (2) chip select high to deep power-down 3 s t rdpd (2) chip select high to standby mode 3 s
30 3588c?dflash?04/06 at26f004 note: 1. not 100% tested (value guaranteed by design and characterization). 12.7 input test waveforms and measurement levels t r , t f < 2 ns (10% to 90%) 12.8 output test load 12.5 program and erase characteristics symbol parameter min typ max units t bp byte program time 15 s t pp page program time (256 bytes using sequential program mode) 5 ms t blke block erase time 4-kbyte 0.1 0.35 sec. 32-kbyte 0.38 0.65 64-kbyte 0.75 1.0 t chpe chip erase time 610sec. t wrsr (1) write status register time 200 ns 12.6 power-up conditions parameter min max units minimum v cc to chip select low time 50 s power-up device delay before program or erase allowed 10 ms power-on reset voltage 1.5 2.5 v ac dri v i n g le v els ac measureme n t le v el 0.45 v 1.5 v 2.4 v de v ice u n der test 30 pf
31 3588c?dflash?04/06 at26f004 13. ac waveforms figure 13-1. serial input timing figure 13-2. serial output timing figure 13-3. hold timing ? serial input cs si sck so msb high-impedance msb lsb t csls t sckh t sckl t cshs t cshh t ds t dh t cslh t csh cs si sck so t v t sckh t sckl t dis t v t oh cs si sck so t hhh t hls t hlh t hhs hold high-impedance
32 3588c?dflash?04/06 at26f004 figure 13-4. hold timing ? serial output figure 13-5. wp timing for write status register command when sprl = 1 cs si sck so t hhh t hls t hlqz t hlh t hhs hold t hhqx wp si sck so 00 0 high-impedance msb x t wps t wph cs lsb of write status register data byte msb of write status register opcode msb of next opcode
33 3588c?dflash?04/06 at26f004 14. ordering information note: 1. contact atmel for availability. 14.1 green package options (pb/halide-fr ee/rohs compliant) f sck (mhz) ordering code package operation range 33 at26f004-ssu 8s1 industrial (-40 c to 85 c) at26f004-su 8s2 at26f004-mu (1) 8m1-a package type 8s1 8-lead, 0.150? wide, plastic gull wing small outline package (jedec soic) 8s2 8-lead, 0.209? wide, plastic gull wing small outline package (eiaj soic) 8m1-a 8-lead, 6 x 5 mm very thin micro lead-frame package (mlf)
34 3588c?dflash?04/06 at26f004 15. packaging information 15.1 8s1 ? jedec soic 1150 e. cheyenne mtn. blvd. colorado springs, co 80 9 06 title drawing no. r rev. note: 3/17/05 8s 1 , 8-lead (0.150" wide body), plastic gull wing small outline (jedec soic) 8s1 c common dimen s ion s (unit of measure = mm) s ymbol min nom max note a1 0.10 ? 0.25 these drawings are for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances , datums, etc. ? e 1 n top view c e1 e 1 end view a b l a1 a 1 e d side view
35 3588c?dflash?04/06 at26f004 15.2 8s2 ? eiaj soic 2325 orchard parkway san jose, ca 9 5131 title drawing no. r rev. 8s 2 , 8-lead, 0.20 9 " body, plastic small outline package (eiaj) 4/7/06 8s2 d common dimen s ion s (unit of measure = mm) s ymbol min nom max note notes: 1. this drawing is for general information only; refer to eiaj drawing edr-7320 for additional information. 2. mismatch of the upper and lower dies and resin burrs are not included. 3. it is recommended that upper and lower cavities be equal. if they are different, the larger dimension shall be regarded. 4. determines the true geometric position. 5. values b,c apply to plated terminal. the standard thickness of the plating layer shall measure between 0.007 to .021 mm. a 1.70 2.16 a1 0.05 0.25 b 0.35 0.48 5 c 0.15 0.35 5 d 5.13 5.35 e1 5.18 5.40 2, 3 e 7.70 8.26 l 0.51 0.85 0 8 e 1.27 bsc 4 1 n e top view t o p v i e w c e1 e 1 end view e n d v i e w a b l a1 a 1 e d side view s i d e v i e w
36 3588c?dflash?04/06 at26f004 15.3 8m1-a ? mlf 2325 orchard parkway san jose, ca 9 5131 title drawing no. r rev. 8 m1-a, 8-pad, 6 x 5 x 1.00 mm body, very thin dual flat package no lead (mlf) a 8m1-a 12/6/04 common dimen s ion s (unit of measure = mm) s ymbol min nom max note a ? 0.85 1.00 a1 ? ? 0.05 a2 0.65 typ a3 0.20 typ b 0.35 0.40 0.48 d 6.00 typ d1 5.75 typ d2 3.20 3.40 3.60 e 5.00 typ e1 4.75 typ e2 3.80 4.00 4.20 e 1.27 l 0.50 0.60 0.75 12 o k 1.30 ref pin 1 id top view pin #1 notch (0.20 r) bottom view d2 e2 l b d1 d e1 e e a3 a2 a1 a 0.08 c 0 s ide view 0 k
37 3588c?dflash?04/06 at26f004 16. revision history revision level ? release date history a ? october 2005 initial release b ? january 2006 changed t cslh parameter for spi mode 3 timing c ? april 2006 changed note 5 of 8s2 package drawing to generalize terminal plating comment
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